EPEEC co-organises BSC/Xilinx training course to simplify heterogeneous programming

On 12-13 February 2019, Barcelona Supercomputing Center (BSC) delivered a joint field-programmable gate array (FPGA) tutorial with Xilinx on the Vivado HLS tool and OmpSs@FPGA programming model. Designed to equip attendees with the skills to program FPGAs, the tutorial was delivered as part of the European projects EPEEC, EuroEXA and LEGaTO.

Providing the performance of hardware with the flexibility of software on a low energy budget, FPGAs are proving popular in a range of applications. This tutorial contributed towards EPEEC’s goal of simplifying programming for heterogeneous architectures, allowing domain application developers to take advantage of the enhanced compute power they provide.

‘With our University Program, Xilinx is helping train the next generation of researchers to get the most out of FPGAs – accelerators which are becoming increasingly common for a wide range computing applications with large datasets, such as genome sequencing,’ said Cathal McCabe, Xilinx University Program Manager for Europe, the Middle East and Africa.

The tutorial, which had 29 attendees from a number of different European countries, focused on the Xilinx tool Vivado HLS and the BSC programming model OmpSs@FPGA, which adapts OmpSs, the BSC technology which allows programs to be executed on multiple processors at once, to FPGAs. Following an exploration of the main aspects of the Vivado HLS optimizations and the OmpSs@FPGA approach, hands-on sessions allowed participants to try HLS Xilinx samples for coding and optimization, focusing on matrix multiplication, RGB – YUV filter and discrete cosine transform (DCT).

‘Principally developed during the AXIOM project, OmpSs@FPGA is a real success story,’ explained Xavier Martorell, leader of the parallel programming models group at BSC. ‘We have delivered a number of tutorials on this technology, and it’s great to see it being improved and used to simplify programming for heterogeneous architectures in European Union-funded projects such as EPEEC, EuroEXA and LEGaTO.’

Unlike other technologies, OmpSs@FPGA allows programmers to exploit multiple processors and accelerators at once, leading to greater efficiency. Thanks to its relatively simple programming interface, the time taken to program FPGA systems – which can be difficult to program – can be dramatically reduced.

The tutorial was one of a series on OmpsS@FPGA for European projects, including the ones held in Barcelona and one at the EuroEXA meeting in Athens in 2018.

X. Martorell at EPEEC training