1st Workshop on Heterogeneous Memory Systems (HMEM)
Online

Collocated with ICS2020

COVID-19

Due to the COVID-19 situation and in coordination with our hosting conference, ICS2020, the workshop will take place online.

Call for Participation

This workshop will serve as a forum to present and discuss ongoing research around heterogeneous memory systems. Topics include, but are not limited to: architectural considerations, middleware, programming models, runtime systems, tools, operating system developments, use cases, early experiences, etc.

This is a traditional-style workshop without formal papers or proceedings. Prospective authors must submit an abstract through this EasyChair link. Authors are also welcome to upload an extended abstract (PDF) for publication in the workshop website in case of acceptance.

Submission deadline: May 29, 2020 AOE.

Registration

Registration is free. Please click here for the registration form.

Agenda

The workshop will take place on 29 June 2020, 15:00 - 19:00 CET.

We will have both invited and contributed talks. The specific agenda is still TBD, but for now we list here the confirmed invited talks:

Seamlessly Embracing Memory Heterogeneity in HPC

João Pedro Barreto, Técnico Lisboa

Abstract: The increasing heterogeneity of the memory hierarchies of today's high-end systems is a tremendous opportunity for improving the efficiency, performance and fault tolerance of memory-intensive HPC applications. As we progress towards Exascale systems, this scenario is greatly amplified. However, in order to fully exploit the virtues of the upcoming heterogeneous memory architectures, we need to deeply rethink the way data is laid out, accessed and managed. One key question that needs to be answered is concerned data placement: at which locations of a heterogeneous memory system should an application place each data object?
This is one of the key problems that the EPEEC project addresses. In order to retain programming productivity, it is desirable that data placement is optimized without requiring disruptive changes to applications. This talk will present our main achievements and results on addressing the problem of data placement at the operating system's kernel level. The main goal is to seamlessly optimize the placement of the memory pages that HPC applications allocate and access. We will focus on two main scenarios: page placement for multi-socket NUMA systems; and page placement with hybrid memory systems combining DRAM with the Intel Optane persistent memory.

Bio: João Barreto is an Assistant Professor at the Computer and Information Systems Department at IST, where he received his Ph.D. degree in 2009. He is a senior researcher at INESC-ID since 2001, and his research interests are parallel and distributed systems and operating systems, in particular: concurrent programming, transactional memory, optimistic replication, and distributed data deduplication. He has participated in a number of international projects, including H2020 projects Cloud-TM and TRACE (as Technical Coordinator) and currently leads the INESC-ID team at the EPEEC project. He is author or co-author of over 25 peer-reviewed scientific publications, including a best paper award at the ACM/IFIP/USENIX 13th International Middleware Conference, and he has served as reviewer on a number of top international conferences and journals.

Libmemkind - Heap Manager for Heterogeneous Memory Architectures

Michal Biesek, Intel

Abstract: Dynamic evolution of random-access memory in recent years brought the hardware table memories with various characteristics. New types of memory like MCDRAM or Intel® Optane™ DC persistent memory gave us new possibilities but also new challenges. The solution to some of those challenges is a memkind library. Existing applications could benefit from a diversity of memory technologies – the combination of various memories could be easily handled and managed by libmemkind. I will be talking about the current status of the memkind library, its possibilities and what the future holds in store for it.

Bio: Michal Biesek is a software engineer in Intel Corporation's Non-Volatile Memory Solution Group since 2018. His area of expertise lies in a volatile usage of persistent memory and enabling existing applications to persistent memory. He is also a lead developer in libmemkind project. Michal holds a master's degree in Electronics and Telecommunications from the Gdańsk University of Technology, Poland.

Abstractions for Data Management in Heterogeneous Systems

Tim Dykes, Hewlett Packard Enterprise (HPE)

Abstract: Heterogeneity is one of the key problems for application developers aiming to efficiently exploit emerging exascale HPC systems. Memory subsystems are becoming increasingly complex, from NUMA concerns in traditional cache hierarchies to the growing number of accelerator or coprocessor devices with on-board memory, and on- and off-node intermediate storage for data staging. The EPiGRAM-HS H2020 project aims to address such concerns from a programming environment perspective with intertwined efforts focusing on Network, Memory, and Compute combined with a set of pilot applications from a variety of scientific domains. We will present our ongoing efforts in the memory-focused work package on the Mamba library, an array-based abstraction for application programmers to transparently allocate, move, and access data efficiently on heterogeneous memory systems.

Bio: Tim Dykes is a Research Engineer working in the HPE HPC & AI EMEA Research Lab, which he joined in 2018. He leads the memory-focused work package of the EPiGRAM-HS project funded by the EC H2020 initiative. His research interests include heterogeneous high-performance architectures, software and compiler optimization, application coupling, computer graphics and scientific visualization. He holds a Ph.D. in Scientific Visualisation from the University of Portsmouth, UK.

An Ecosystem of Tools for Broad Heterogeneous Memory Usage

Marc Jordà, Barcelona Supercomputing Center (BSC)

Abstract: Since providing the required amount of memory for upcoming exascale applications is non-viable by means of top-performance technology only, due to energy consumption and dissipation constraints, vendors are incorporating a variety of additional memory subsystems built upon different technologies, which provide diverse features and limitations (e.g., Intel’s Optane DC Persistent Memory). Deciding what data to host in each memory subsystem is far from trivial and poses notable performance implications. Recent research has focused on their use for specific purposes such as resilience or to host selected data objects based on some basic criteria. The aim of this Intel-BSC collaboration is to move a big step forward and develop technology to build an innovative generic software ecosystem to facilitate the efficient use of heterogeneous memory systems, what will be crucial to leverage the full potential of exascale platforms. We will present the developed software ecosystem and our early performance analysis.

Bio: Marc Jordà is a Research Engineer at the Barcelona Supercomputing Center (BSC), working in the Accelerators and Communications for HPC team. He is part of the Intel-BSC Exascale Laboratory, where he collaborates in this project with Antonio J. Peña (BSC) and Harald Servat (Intel). His interests include performance tuning for heterogeneous memory systems, GPU-enabled applications, and deep learning frameworks.

Organizers

General Chairs

Antonio J. Peña, Barcelona Supercomputing Center (BSC)

Harald Servat, Intel

Steering Committee

Marie-Christine Sawley, Intel

Jesus Labarta, Barcelona Supercomputing Center (BSC)

Eduard Ayguadé, Barcelona Supercomputing Center (BSC)